Verilog Neural Network Accelerator for Digit Recognition

An 8-bit integer multilayer perceptron (784-32-10) is trained on MNIST and built in synthesisable Verilog as a multiply-accumulate datapath with a finite-state machine, then verified the way AI chips are verified: the RTL must equal a bit-exact software golden model, value by value and clock by clock. The float model reaches 96.17 % on the 10,000 MNIST test images, inside the 96-97 % the spec expects; the 8-bit integer model is 0.07 points above the float model on the test images, within the spec's 0.5 points. In Icarus Verilog 0 of 15,056 simulated images differ from the Python fixed-point model in any digit, hidden value or score (10,000 MNIST test images on the 1-MAC core), and 0 of 513,220 clock rows differ from the Python cycle model (20 images, 1 MAC). One image takes 25,661 clocks on the one-lane core. Yosys maps the core to 357 LUT4, 301 flip-flops, 14 block RAM and 1 DSP on a Lattice ECP5 (tool estimates); no board was used and no power figure exists. No other finished project in this series uses MNIST or Verilog: E10, E11 and E12 ask which software classifier wins, this project asks whether a fixed-point circuit does exactly what the model says, in how many clocks, in how much logic.

Category: Electronics and Communication Engineering

Electronics & Communication Engineering Project E13 from ProTechSC Academy, with graphical abstract, video demonstration and project guidance.